It is common to have one input and output device on a single large scale integration (LSI) circuit to include peripheral input output interfaces, direct memory access controllers (DMAC), memory controllers and processor interfaces in the system where the processor and the peripheral input and output devices share a common memory. One way to debug the DMAC operations of the input and output devices includes event detection by comparing an address to a predetermined address as proposed in Japanese Patent Publication Hei 6-35750. In tracing an address for access, although a debug device using an external trace memory is know for the processor, it is generally not practiced to trace the addresses that the DMAC accesses since the access consumes the trace memory.
After the image data is read from the memory and the image is rotated, a device such as a printer has a direct memory access that the image data is again written in the memory. When the image is rotated, for the operational efficiency there is a situation where the memory is not accessed in a simple ascending order. In this situation, when it is debugged, it is desired to trace the DMC access. However, since a general tracer needs a separate trace memory for debugging and the amount of data exceeds the trace for the memory access by the processor, the manufacturing cost of the debugger is undesirably high.
Furthermore, when an illegal DMA memory access is detected or the data written in memory is referred, it is difficult to have an expected value for capacity in the device such as LSI. It is necessary to have a relatively large debugging device that is operationally associated with the trace memory. The debugger cost is further increased.
Based upon the above described reasons, it still remains desirable to debug in an efficient manner at a low cost without placing an external debugger.